Integrated circuits are usually fabricated with a multiplicity of patterned metallization or interconnect planes which are electrically isolated from one another by dielectric intermediate insulating layers. In order to realize electrical connections between the patterned metallization or interconnect layers or between the interconnect layers and a substrate, contact holes or vias are formed in the insulating layer at selected locations.
In the context of advancing integration density, in order to realize improved performance features such as increased speed and increased circuit functionality per unit area, the feature sizes and, in particular, the contact holes or vias are becoming increasingly smaller. This leads to the contact holes or vias becoming increasingly susceptible to stress migration.
In contrast to electromigration, in which a mass transport of interconnect material is brought about on account of a direct current that is present and at very high current densities, stress migration relates to a mass transport which is brought about in interconnect layers or contact holes in particular on account of mechanical stresses or stress gradients. Such mechanical stresses, which originate for example from a mismatch of thermal expansion coefficients and of different moduli of elasticity of the interconnect layers or the insulator layers lying in between and other conductive and nonconductive intermediate layers, accordingly lead to a similar material transport, which, depending on a compressive or tensile stress or alternating stress, brings about the formation of voids in the electrically conductive material. As a result, an electrical resistance of interconnects in the semiconductor module may be increased or even an interconnect interruption may occur.
If a fabrication process is considered, by way of example, in which, on an interconnect layer (aluminum, copper etc.) formed on a semiconductor substrate or a dielectric layer, a further insulator layer is deposited, for example at a temperature of 350 degrees Celsius by means of a CVD (Chemical Vapor Deposition) method, the different expansion coefficients between the interconnect layer and the adjoining insulating layers already give rise to mechanical stresses which bring about a stress migration in the interconnect layer. In the case of copper metallization with Cu vias, stress gradients e.g. on account of thermal mismatch lead to the transport of vacancies into the via (formation of voids). In other words, vacancies diffuse to reduce the stress energy in the interconnect layer. As a result, after a certain time, usually several months or years, this mass transport in the interconnect layer or the vias produces voids which influence the electrical properties of the semiconductor module and may lead as far as an interruption of an interconnect.
FIGS. 1A to 1C show simplified sectional views for illustrating conventional devices for detecting stress migration properties.
In accordance with FIG. 1A, reliability examinations for characterizing the above-described stress migration properties of interconnects and in particular of metallizations in integrated circuits or semiconductor modules IC are usually carried out directly on the wafer or at the wafer level. In this case, the resistances of various stress migration test structures SMT which are formed in a semiconductor module IC are measured at regular intervals (e.g. once per hour, day or week) and the deviation from the initial value is assessed. Between these measurements, the wafers are stored in a furnace at temperatures of greater than 150 degrees Celsius. As a result, the duration for these reliability examinations can be significantly reduced to about 1000 to 2000 hours in order to cover a product service life of e.g. 15 years.
However, in the case of a test device of this type, the results obtained are only inadequate on account of a lack of final mounting in a housing and, in this respect, do not enable a sufficiently accurate detection of the stress migration properties of the semiconductor module in an environment close to the product.
In accordance with FIG. 1B, a test of this type may accordingly also be carried out in a finally mounted test housing TG, the semiconductor module IC being mounted on a module carrier T by means of bonding wires or soldering connections B, for example, a thermostable ceramic test housing being used as the housing. Although it is possible in this way to detect and assess not only internal stresses σ0 of the semiconductor module IC but also the stresses σTG caused by the mounting or the soldering connections B and the module carrier T of the test housing TG, examination results of this type again do not yield accurate statements for the stress migration properties of the interconnect systems in a semiconductor module with a product housing, in particular on account of the test housing TG deviating from a product-relevant housing.
In accordance with FIG. 1C, the semiconductor module IC to be examined may also be embedded in a product-relevant plastic housing G once again by means of soldering connections B and a module carrier T. However, in this case corresponding heating to temperatures TE of greater than 150 degrees Celsius, the thermal mismatch of the layers surrounding the interconnect system causes a change in the product-relevant stress state. Accordingly, accurate statements concerning the stress migration properties in a semiconductor module IC packaged in this way are not obtained. Furthermore, the plastic composition of the housing G may also melt or soften, as a result of which the stress caused by this plastic housing G likewise leads to a reduced stress σG′.
Without these elevated temperatures of greater than 150 degrees Celsius, which are preferably generated by an external heating coil EH, reliability examinations of this type cannot be carried out economically, however, since they would take several months and usually even several years.